The present invention is generally related to integrated logic circuits and, more particularly, to an improved circuit design technique for Schottky transistor logic (STL) and integrated Schottky logic (ISL).
Low-power Schottky transistor-transistor logic (TTL) and integrated injection logic (I.sup.2 L) gates are well-known integrated circuits which can be easily produced. Although I.sup.2 L has several advantages, the foremost being its high packing density and low power consumption, its speed is often too slow for many applications. In contrast, low power Schottky TTL is characterized by high speed performance but high power consumption and low packing density. The performance gap created by these two logic families led recently to the development of STL and ISL.
STL, as illustrated in FIG. 1, is a non-saturating bipolar circuit form wherein each gate is a single-input, multiple-output inverter which includes a clamping Schottky diode between the base and collector of the NPN transistor used in the gate. In order for the STL gate to provide a logic swing, however, the Schottky diodes in the gate output circuit must have a different barrier height than that of the clamping Schottky diode. STL gates are, therefore, not easily made by standard fabrication techniques which utilize only one type of Schottky diode.
ISL, as illustrated in FIG. 2, is a saturating bipolar circuit form wherein each gate is a single-input, multiple-output inverter wherein the Schottky clamping diode of STL is replaced by a somewhat slower, silicon clamp device, such as a PNP transistor. Although ISL gates are not as fast as STL gates, the devices can be easily fabricated using existing processes. Both types of Schottky logic gates, however, are much faster than I.sup.2 L and have higher packing densities and lower power consumption than Schottky TTL.
A problem arises, however, in the use of STL or ISL circuit designs when it becomes desirable to tie individual gate inputs to a common line, as illustrated in FIG. 3. This interconnection may be required to increase fan-out or reduce the number of metal interconnect stripes used in the circuit. However, when the STL or ISL gate inputs are tied together, severe current hogging and logic faults readily occur, making the design impractical. Therefore, initial attempts at using STL or ISL with a common-base connection have been unsuccessful.